地线位置对CMOS互连性能的影响

64th ARFTG Microwave Measurements Conference, Fall 2004. Pub Date : 2004-12-02 DOI:10.1109/ARFTGF.2004.1427600

M.F. Ktata, U. Arz, H. Grabinski, H. Fischer

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引用次数: 1

摘要

我们研究了地线位置的影响，以及不同电导率(10 S/m(低)、100 S/m(中)和10 000 S/m(高))的导电基板对片上互连的影响。通过特殊设计的测试结构的双端口网络分析仪测量，在高达50 GHz的频率范围内验证了从现场计算获得的特征线路参数。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Impact of ground line position on CMOS interconnect behavior

We investigate the impact of ground line position as well as the effects of conductive substrates with different conductivities of 10 S/m (low), 100 S/m (medium) and 10.000 S/m (high) on on-chip interconnects. Characteristic line parameters obtained from field calculations are validated with two-port network analyzer measurements of specially designed test structures in a frequency range up to 50 GHz.

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64th ARFTG Microwave Measurements Conference, Fall 2004.

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