下一代晶圆级芯片规模的可靠性分析

2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) Pub Date : 2013-04-14 DOI:10.1109/EUROSIME.2013.6529987

Qiuxiao Qian, Y. Liu

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引用次数: 5

摘要

本文通过建模对下一代WLCSP的可靠性性能进行了研究。从单凸点设计到封装尺寸设计，再到PCB板的应用设计，进行了深入的研究。对聚酰亚胺、不同宽度和长度比的焊点阵列布局和PCB板通孔布局进行了仿真，以提高可靠性性能。对不同聚酰亚胺布局和不同材料的模型进行了热循环和跌落试验研究。然后，研究了不同凹凸阵宽度和长度比对下一代WLCSP可靠性性能的影响。最后，在热循环测试中分析了不同PCB板设计和布局对下一代WLCSP可靠性性能的影响。研究了PCB板上不同的通孔和盲孔阵列。

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Reliability analysis of next generation wafer level chip scale

In this paper, the reliability performance of next generation WLCSP is studied through modeling. Intensive study is carried out from single bump design to package dimension design and the application design in PCB board. Polyimide, solder joint array layout with different width and length ratio and the PCB board via layout are simulated to improve the reliability performance. The models with different polyimide layouts and different material are studied in both thermal cycling and drop test. Then, the impact of different bump array width and length ratio on the next generation of the WLCSP is studied for the reliability performance. Finally, the impact of different PCB board via design and layout on the reliability performance of next generation WLCSP is analyzed in thermal cycling test. Different through board vias and blind vias array in PCB board are studied.

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来源期刊

2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)

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