Area and performance evaluation of central DMA controller in Xilinx embedded FPGA designs

Real-time processing of a large amount of data is required in every digital signal processing task performed on FPGAs. Efficient, high throughput and low overhead transfer of data between sub-modules in an FPGA based embedded system can be a challenging problem. Availability of soft and hard CPU cores, their related infrastructure and development tools for FPGAs, provide us with the possibility of creating a complete system on a single FPGA. Different DMA transfer techniques provide sub-modules with the possibility of high performance data transfer without CPU intervention. Focusing on Xilinx FPGA devices which contain PowerPC hard CPU core, we have performed a detailed study of a DMA transfer technique based on central management of data movements. Data transfer performance of the system is evaluated carefully in different scenarios, thus proving the effectiveness of exploiting central DMA controller in practical applications. Linux is the dominant OS in most of FPGA based embedded systems. Simplified management and utilization of central DMA transfers can become feasible by the means of suitable kernel mode drivers. We have developed required building elements of such low level driver.