{"title":"利用伽罗瓦域运算的HLS和HDL实现效率比较","authors":"A. Stanciu, C. Gerigan","doi":"10.1109/SIITME.2017.8259883","DOIUrl":null,"url":null,"abstract":"The paper presents a comparative analysis between the implementations of the important operation over Galois Fields GF(2n): division and multiplication. The analysis focuses on the comparison of HLS (High Level Synthesis) and HDL (Hardware Description Language) implementations in the following areas: the size of the implemented digital circuit; the frequency and the latency of the design; how straightforward is the implementation and how simple is to modify the design.","PeriodicalId":138347,"journal":{"name":"2017 IEEE 23rd International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Comparison between implementations efficiency of HLS and HDL using operations over Galois Fields\",\"authors\":\"A. Stanciu, C. Gerigan\",\"doi\":\"10.1109/SIITME.2017.8259883\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a comparative analysis between the implementations of the important operation over Galois Fields GF(2n): division and multiplication. The analysis focuses on the comparison of HLS (High Level Synthesis) and HDL (Hardware Description Language) implementations in the following areas: the size of the implemented digital circuit; the frequency and the latency of the design; how straightforward is the implementation and how simple is to modify the design.\",\"PeriodicalId\":138347,\"journal\":{\"name\":\"2017 IEEE 23rd International Symposium for Design and Technology in Electronic Packaging (SIITME)\",\"volume\":\"88 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE 23rd International Symposium for Design and Technology in Electronic Packaging (SIITME)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIITME.2017.8259883\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 23rd International Symposium for Design and Technology in Electronic Packaging (SIITME)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIITME.2017.8259883","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Comparison between implementations efficiency of HLS and HDL using operations over Galois Fields
The paper presents a comparative analysis between the implementations of the important operation over Galois Fields GF(2n): division and multiplication. The analysis focuses on the comparison of HLS (High Level Synthesis) and HDL (Hardware Description Language) implementations in the following areas: the size of the implemented digital circuit; the frequency and the latency of the design; how straightforward is the implementation and how simple is to modify the design.