基于netfpga的OpenFlow交换机上WFQ算法的硬件高效实现

2016 International Conference on Advanced Technologies for Communications (ATC) Pub Date : 2016-10-01 DOI:10.1109/ATC.2016.7764821

Hải Trần Thị Hồng, Quy Bien Xuan, Duong Doan Van, N. P. Ngoc, Thanh Tam Nguyen Huu

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引用次数: 2

摘要

网络业务的发展使其对带宽的要求越来越高、越来越多样化，这导致了服务质量(QoS)的难以保证。提出了一种基于加权公平排队(Weighted Fair Queuing, WFQ)算法的OpenFlow交换机。该系统是在采用Xilinx Virtex II Pro 50技术的NetFPGA 1G板上实现的。结果表明，在目前的实现中，我们的电路可以在8 Gbps的吞吐量下提供足够的QoS水平。由于设计的灵活性，WFQ电路可以针对以后的技术，以提供更高的吞吐量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Hardware-efficient implementation of WFQ algorithm on NetFPGA-based OpenFlow switch

The development of network services makes their requirements for bandwidth become higher and more various, which leads to difficulty in Quality of Service (QoS) guarantee. In this paper, an OpenFlow switch featuring Weighted Fair Queuing (WFQ) algorithm is proposed. The system is implemented into NetFPGA 1G board which utilizes Xilinx Virtex II Pro 50 technology. The results have shown that our circuit can deliver adequate level of QoS at a throughput of 8 Gbps in its current implementation. Due to the flexibility of the design, the WFQ circuit can be targeted for later technologies in order to provide higher throughput.

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2016 International Conference on Advanced Technologies for Communications (ATC)

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