一种用于标准CMOS技术的基于环形单聚EPROM单元的新型存储阵列

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-10 DOI:10.1109/MTDT.2002.1029775

C. Dray, P. Gendrier

{"title":"一种用于标准CMOS技术的基于环形单聚EPROM单元的新型存储阵列","authors":"C. Dray, P. Gendrier","doi":"10.1109/MTDT.2002.1029775","DOIUrl":null,"url":null,"abstract":"Within the scope of non-volatile memories, CMOS compatibility and portability are serious issues. We describe here an edgeless single-poly floating gate p-channel memory cell, which can be embedded into a novel memory array architecture. It features high electrical performance together with a robustness with respect to the process. It has been processed in a 0.18 /spl mu/m HCMOS technology from STMicroelectronics, Crolles.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A novel memory array based on an annular single-poly EPROM cell for use in standard CMOS technology\",\"authors\":\"C. Dray, P. Gendrier\",\"doi\":\"10.1109/MTDT.2002.1029775\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Within the scope of non-volatile memories, CMOS compatibility and portability are serious issues. We describe here an edgeless single-poly floating gate p-channel memory cell, which can be embedded into a novel memory array architecture. It features high electrical performance together with a robustness with respect to the process. It has been processed in a 0.18 /spl mu/m HCMOS technology from STMicroelectronics, Crolles.\",\"PeriodicalId\":230758,\"journal\":{\"name\":\"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)\",\"volume\":\"71 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-07-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.2002.1029775\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2002.1029775","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

在非易失性存储器的范围内，CMOS的兼容性和可移植性是严重的问题。我们在这里描述了一种无边的单多浮栅p通道存储单元，它可以嵌入到一种新的存储阵列架构中。它具有高电气性能以及相对于工艺的稳健性。它采用意法半导体(STMicroelectronics, Crolles)的0.18 /spl mu/m HCMOS技术处理。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A novel memory array based on an annular single-poly EPROM cell for use in standard CMOS technology

Within the scope of non-volatile memories, CMOS compatibility and portability are serious issues. We describe here an edgeless single-poly floating gate p-channel memory cell, which can be embedded into a novel memory array architecture. It features high electrical performance together with a robustness with respect to the process. It has been processed in a 0.18 /spl mu/m HCMOS technology from STMicroelectronics, Crolles.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)

自引率

0.00%

发文量