采用直接电子束光刻技术制备的22ns 4k位SRAM

P. Shah, G. Pollack, G. Varnell, C. Rhodes, D. Kang, W. Bruncke
{"title":"采用直接电子束光刻技术制备的22ns 4k位SRAM","authors":"P. Shah, G. Pollack, G. Varnell, C. Rhodes, D. Kang, W. Bruncke","doi":"10.1109/IEDM.1980.189952","DOIUrl":null,"url":null,"abstract":"A 22 ns scaled 4K-bit static RAM (SRAM) has been fabricated on a 12K mil2chip demonstrating high density electron beam direct slice writing lithography and dry etch processes. This 2 µm design rule, LSI vehicle used a vector-scanned electron-beam exposure system with a capability of 2 µm feature definition, 0.25 µm level-to-level registration, and auto chip-by-chip alignment. High speed, high resolution positive and negative electron-beam resists were used for all patterning steps. All implanted scaled MOS process with dry etching techniques for Si, SiO2, and Si3N4were used to realize 22ns access time 4KSRAM at full temperature. A gate delay of 0.18ns and a speed power product of 0.08 pJ were realized on a 1 µm channel ring oscillator with this process.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 22ns 4K-bit SRAM fabricated with direct electron beam lithography\",\"authors\":\"P. Shah, G. Pollack, G. Varnell, C. Rhodes, D. Kang, W. Bruncke\",\"doi\":\"10.1109/IEDM.1980.189952\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 22 ns scaled 4K-bit static RAM (SRAM) has been fabricated on a 12K mil2chip demonstrating high density electron beam direct slice writing lithography and dry etch processes. This 2 µm design rule, LSI vehicle used a vector-scanned electron-beam exposure system with a capability of 2 µm feature definition, 0.25 µm level-to-level registration, and auto chip-by-chip alignment. High speed, high resolution positive and negative electron-beam resists were used for all patterning steps. All implanted scaled MOS process with dry etching techniques for Si, SiO2, and Si3N4were used to realize 22ns access time 4KSRAM at full temperature. A gate delay of 0.18ns and a speed power product of 0.08 pJ were realized on a 1 µm channel ring oscillator with this process.\",\"PeriodicalId\":180541,\"journal\":{\"name\":\"1980 International Electron Devices Meeting\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1980 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1980.189952\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1980.189952","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

在12K芯片上制备了一个22ns缩放的4k位静态RAM (SRAM),演示了高密度电子束直接切片刻蚀和干蚀刻工艺。这种2微米设计规则,LSI车辆使用矢量扫描电子束曝光系统,具有2微米特征定义,0.25微米级对级配准和自动逐芯片对准的能力。高速,高分辨率的正负电子束电阻用于所有的图像化步骤。采用硅、SiO2和si3n4的干法刻蚀工艺,在室温下实现了22ns的4KSRAM。在1µm通道环形振荡器上实现了0.18ns的门延迟和0.08 pJ的速度功率积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 22ns 4K-bit SRAM fabricated with direct electron beam lithography
A 22 ns scaled 4K-bit static RAM (SRAM) has been fabricated on a 12K mil2chip demonstrating high density electron beam direct slice writing lithography and dry etch processes. This 2 µm design rule, LSI vehicle used a vector-scanned electron-beam exposure system with a capability of 2 µm feature definition, 0.25 µm level-to-level registration, and auto chip-by-chip alignment. High speed, high resolution positive and negative electron-beam resists were used for all patterning steps. All implanted scaled MOS process with dry etching techniques for Si, SiO2, and Si3N4were used to realize 22ns access time 4KSRAM at full temperature. A gate delay of 0.18ns and a speed power product of 0.08 pJ were realized on a 1 µm channel ring oscillator with this process.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信