Hysteresis of intrinsic I/sub DDQ/ currents

Empirical analyses of the IDDQ signatures of 0.18 p m devices indicate that IDDQ currents exhibit hysteresis. A newly proposed test method, SPIRIT (Single Pattern Iteration lDDQ Test), demonstrates that the test pattern and the device clock speed before measurements must be maintained to assure the integrity of IDDe measurements, which is the fundamental assumption of IDDQ applications: testing, diagnosis, monitoring, and static power estimation. Newly proposed IDDQ signature and hysteresis models show that hysteresis phenomena are caused by the global transient threshold voltage shifts induced by the direct tunnel charges to the pre-existing border traps under nominal operating conditions.