Relevance of off-state NBTI degradation in depletion HVNMOS transistor for power application

For the reliability assessment of HV depletion NMOS devices, the relevant off-state degradation mechanisms are discussed and quantified on the example of a transistor in a 130 nm power technology. It can be shown that depending on its construction, the transistor can suffer from combined gate and drain voltage stress and that the observed $\mathrm{V}_{\mathrm{t}\mathrm{h}}$ shifts have to be attributed exclusively to the NBTI effect. Furthermore, it is explained by considering possible circuit applications that this NBTI degradation mechanism can be critical causing significant leakage increase or even unintended device turn-on over lifetime. Finally, as a prevention measure, fluorine implantation into the gate oxide for improving the device reliability with respect to the NBTI effect is investigated.