基于FPGA的BRAM高效多端口存储器

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI:10.1109/VLSI-DAT.2015.7114526

J. Lin, B. Lai

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引用次数: 9

摘要

多端口存储器广泛应用于现代fpga设计中。然而，在FPGA上实现多端口存储器对bram的过度需求将阻碍bram在设计的其他部分的使用。这个问题成为一个严重的问题，特别是对于需要巨大的内部存储容量的设计。本文提出了一种增加读端口和写端口的高效BRAM方案。与以前的工作相比，所提出的多端口存储器可以减少高达53%的对bram的要求，并且只有轻微的频率下降。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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BRAM efficient multi-ported memory on FPGA

Multi-ported memory is broadly used in modern designs on FPGAs. However, the excessive demand on BRAMs to implement multi-ported memory on FPGA would block the usage of BRAMs for other parts of a design. This issue becomes a serious concern especially for designs that require huge internal storage capacity. This paper proposes a BRAM efficient scheme on increasing read ports and write ports. When compared with previous works, the proposed multi-ported memory can reduce up to 53% requirement on BRAMs with only minor frequency degradation.

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VLSI Design, Automation and Test(VLSI-DAT)

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