Spatial and temporal scheduling of clock arrival times for IR hot-spot mitigation, reformulation of peak current reduction

This paper, formulates a novel technique that explores on-chip IR drop reduction and instantaneous demanded peak-current reduction simultaneously. Proposed solution leverages unused timing slacks, and schedules the clock arrival times to relax the peak current which is delivered through each via-stack in the on-chip IR hot-spots. In addition, this paper formulates and introduces a new evaluation metric which aids us in assessing the improvement in the voltage-noise gaurdband after application of the proposed mitigation technique. The strength of the proposed IR mitigation technique is that, in addition to timing information, it considers the power delivery network and cell placement information while scheduling the clock arrival times to achieve the best results. Application of the proposed solution to a selected IWLS benchmarks reduces the peak dynamic IR-drop by ∼49%, and the peak demanded current by ∼44%.