{"title":"基于开关控制电阻器的CMOS PGA直流偏置抵消无线传感器网络射频芯片","authors":"Fan Xiang-ning, Cheng Da, F. Yangyang","doi":"10.1109/ISSSE.2010.5607070","DOIUrl":null,"url":null,"abstract":"In this paper, a programmable gain amplifier (PGA) for wireless sensor network (WSN) is proposed and implemented using 0.18μm CMOS process. A fully differential feedback configuration is adopted, and the variable gains are achieved by switch controlled resistor (SCR) network. DC feedback technique is also utilized to eliminate the DC offset. SCR network layout design is essential to maintain the accuracy of the gain value under process variations. Local and global common centroid symmetric layout techniques are applied to ensure the matching of the resistors in SCR network. Post-simulation results show that the PGA has 0dB∼60dB variable gain range and 1dB gain resolution; the minimum DC attenuation is 20dB over whole gain range; the pass-band range is 10.8Hz∼20.15MHz under most gain configurations; output swing is 1.4V; and the PGA consumes 3.7mA current with 1.8V supply voltage. Chip measurement results show that the PGA can achieve 2.23dB∼56.66dB variable gain range after minor bias voltage adjustment; and the total current it consumes is about 5.2mA.","PeriodicalId":211786,"journal":{"name":"2010 International Symposium on Signals, Systems and Electronics","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A switch controlled resistor based CMOS PGA with DC offset cancellation for WSN RF chip\",\"authors\":\"Fan Xiang-ning, Cheng Da, F. Yangyang\",\"doi\":\"10.1109/ISSSE.2010.5607070\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a programmable gain amplifier (PGA) for wireless sensor network (WSN) is proposed and implemented using 0.18μm CMOS process. A fully differential feedback configuration is adopted, and the variable gains are achieved by switch controlled resistor (SCR) network. DC feedback technique is also utilized to eliminate the DC offset. SCR network layout design is essential to maintain the accuracy of the gain value under process variations. Local and global common centroid symmetric layout techniques are applied to ensure the matching of the resistors in SCR network. Post-simulation results show that the PGA has 0dB∼60dB variable gain range and 1dB gain resolution; the minimum DC attenuation is 20dB over whole gain range; the pass-band range is 10.8Hz∼20.15MHz under most gain configurations; output swing is 1.4V; and the PGA consumes 3.7mA current with 1.8V supply voltage. Chip measurement results show that the PGA can achieve 2.23dB∼56.66dB variable gain range after minor bias voltage adjustment; and the total current it consumes is about 5.2mA.\",\"PeriodicalId\":211786,\"journal\":{\"name\":\"2010 International Symposium on Signals, Systems and Electronics\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Symposium on Signals, Systems and Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSSE.2010.5607070\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Symposium on Signals, Systems and Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSSE.2010.5607070","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A switch controlled resistor based CMOS PGA with DC offset cancellation for WSN RF chip
In this paper, a programmable gain amplifier (PGA) for wireless sensor network (WSN) is proposed and implemented using 0.18μm CMOS process. A fully differential feedback configuration is adopted, and the variable gains are achieved by switch controlled resistor (SCR) network. DC feedback technique is also utilized to eliminate the DC offset. SCR network layout design is essential to maintain the accuracy of the gain value under process variations. Local and global common centroid symmetric layout techniques are applied to ensure the matching of the resistors in SCR network. Post-simulation results show that the PGA has 0dB∼60dB variable gain range and 1dB gain resolution; the minimum DC attenuation is 20dB over whole gain range; the pass-band range is 10.8Hz∼20.15MHz under most gain configurations; output swing is 1.4V; and the PGA consumes 3.7mA current with 1.8V supply voltage. Chip measurement results show that the PGA can achieve 2.23dB∼56.66dB variable gain range after minor bias voltage adjustment; and the total current it consumes is about 5.2mA.