{"title":"片上分组交换网络的调度方法","authors":"Y. Salah, M. Zeghid, I. Bennour, R. Tourki","doi":"10.1109/CCCA.2011.6031503","DOIUrl":null,"url":null,"abstract":"Performance constraints imposed on the on-Chip System (SoC) design require efficiency and predictability of inter-core communication part in system. This implies the Quality-of-Service (QoS) requirement assurance for the communication. The current work presents a novel approach that borrows three Real-Time Operating System (RTOS) scheduling algorithms and adapts them to Networks-on-Chip (NoCs). This technique is designed specifically for multimedia and safety-critical real-time applications to reduce contention problem in packet-switched networks and provides QoS guarantees in terms of throughput and end-to-end latency. An HDL implementation of a NoC architecture has been simulated to prove our concept.","PeriodicalId":259067,"journal":{"name":"2011 International Conference on Communications, Computing and Control Applications (CCCA)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A scheduling approach for packet-switched on-chip networks\",\"authors\":\"Y. Salah, M. Zeghid, I. Bennour, R. Tourki\",\"doi\":\"10.1109/CCCA.2011.6031503\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Performance constraints imposed on the on-Chip System (SoC) design require efficiency and predictability of inter-core communication part in system. This implies the Quality-of-Service (QoS) requirement assurance for the communication. The current work presents a novel approach that borrows three Real-Time Operating System (RTOS) scheduling algorithms and adapts them to Networks-on-Chip (NoCs). This technique is designed specifically for multimedia and safety-critical real-time applications to reduce contention problem in packet-switched networks and provides QoS guarantees in terms of throughput and end-to-end latency. An HDL implementation of a NoC architecture has been simulated to prove our concept.\",\"PeriodicalId\":259067,\"journal\":{\"name\":\"2011 International Conference on Communications, Computing and Control Applications (CCCA)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-03-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 International Conference on Communications, Computing and Control Applications (CCCA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCCA.2011.6031503\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Conference on Communications, Computing and Control Applications (CCCA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCCA.2011.6031503","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A scheduling approach for packet-switched on-chip networks
Performance constraints imposed on the on-Chip System (SoC) design require efficiency and predictability of inter-core communication part in system. This implies the Quality-of-Service (QoS) requirement assurance for the communication. The current work presents a novel approach that borrows three Real-Time Operating System (RTOS) scheduling algorithms and adapts them to Networks-on-Chip (NoCs). This technique is designed specifically for multimedia and safety-critical real-time applications to reduce contention problem in packet-switched networks and provides QoS guarantees in terms of throughput and end-to-end latency. An HDL implementation of a NoC architecture has been simulated to prove our concept.