全可编程SoC上的HDMI视频缩放

Chih-Yao Tsai, Chaoxiu Chen
{"title":"全可编程SoC上的HDMI视频缩放","authors":"Chih-Yao Tsai, Chaoxiu Chen","doi":"10.1109/ICCPS.2016.7751118","DOIUrl":null,"url":null,"abstract":"We propose a High-Definition Multimedia Interface (HDMI) video scaling system based on an all-programmable SoC, which can be used in any image processing system requiring a two-dimensional (2D) interpolation accelerator. This structure work on a platform-based SoC environment. By the AXI Video Direct Memory Access (AXI VDMA), video data are directly transferred between DDR3 memory and the built-in FPGA where the proposed buffering scheme and interpolation accelerator are implemented. We store video data in the DDR3 memory and the interpolation accelerator performs real-time video scaling. An experiment with HDMI video input from a Microsoft Windows PC and HDMI video output to another display proves the effectiveness of the real-time video scaling.","PeriodicalId":348961,"journal":{"name":"2016 International Conference On Communication Problem-Solving (ICCP)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"HDMI video scaling on an all-programmable SoC\",\"authors\":\"Chih-Yao Tsai, Chaoxiu Chen\",\"doi\":\"10.1109/ICCPS.2016.7751118\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a High-Definition Multimedia Interface (HDMI) video scaling system based on an all-programmable SoC, which can be used in any image processing system requiring a two-dimensional (2D) interpolation accelerator. This structure work on a platform-based SoC environment. By the AXI Video Direct Memory Access (AXI VDMA), video data are directly transferred between DDR3 memory and the built-in FPGA where the proposed buffering scheme and interpolation accelerator are implemented. We store video data in the DDR3 memory and the interpolation accelerator performs real-time video scaling. An experiment with HDMI video input from a Microsoft Windows PC and HDMI video output to another display proves the effectiveness of the real-time video scaling.\",\"PeriodicalId\":348961,\"journal\":{\"name\":\"2016 International Conference On Communication Problem-Solving (ICCP)\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Conference On Communication Problem-Solving (ICCP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCPS.2016.7751118\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference On Communication Problem-Solving (ICCP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCPS.2016.7751118","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

我们提出了一种基于全可编程SoC的高清多媒体接口(HDMI)视频缩放系统,该系统可用于任何需要二维插值加速器的图像处理系统。这种结构适用于基于平台的SoC环境。通过AXI视频直接存储器访问(AXI VDMA),视频数据在DDR3存储器和内置FPGA之间直接传输,FPGA实现了所提出的缓冲方案和插值加速器。我们将视频数据存储在DDR3存储器中,插值加速器执行实时视频缩放。通过HDMI视频从一台微软Windows PC机输入,再输出到另一台显示器的实验,验证了实时视频缩放的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
HDMI video scaling on an all-programmable SoC
We propose a High-Definition Multimedia Interface (HDMI) video scaling system based on an all-programmable SoC, which can be used in any image processing system requiring a two-dimensional (2D) interpolation accelerator. This structure work on a platform-based SoC environment. By the AXI Video Direct Memory Access (AXI VDMA), video data are directly transferred between DDR3 memory and the built-in FPGA where the proposed buffering scheme and interpolation accelerator are implemented. We store video data in the DDR3 memory and the interpolation accelerator performs real-time video scaling. An experiment with HDMI video input from a Microsoft Windows PC and HDMI video output to another display proves the effectiveness of the real-time video scaling.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信