一种基于台积电90nm工艺的栅极氧化击穿抗熔丝OTP ROM阵列

2015 International Symposium on Next-Generation Electronics (ISNE) Pub Date : 2015-05-04 DOI:10.1109/ISNE.2015.7132015

Zicheng Liu, Ruifeng Zheng, Jianwei Sun

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引用次数: 2

摘要

本文介绍了一种利用MOSFET栅极氧化物击穿的一次性可编程(OTP)反熔阻ROM阵列，该阵列采用TSMC 90nm标准CMOS工艺设计和制造。测量了击穿电压和击穿时间。介绍了三晶体管抗熔丝OTP ROM阵列的原理图设计。在实际应用中，采用SPI总线来减少芯片的数量。实验结果表明，该系统可以很好地实现读写功能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A gate-oxide-breakdown antifuse OTP ROM array based on TSMC 90nm process

A one-time programmable (OTP) antifuse ROM array using MOSFET gate oxide breakdown, which is designed and fabricated under TSMC 90nm standard CMOS process, is presented in this paper. The breakdown voltage and breakdown time are measured. The schematic design of three-transistor antifuse OTP ROM array is exhibited. SPI bus is used to decrease the number of chip pads in practice. The experimental result shows that write & read function can be realized successfully.

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2015 International Symposium on Next-Generation Electronics (ISNE)

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