Modeling Power Supply Rejection in Analog Systems

This paper proposes an approach to calculate the Power Supply Rejection (PSR) for a cascade of linear analog blocks. The model facilitates the analysis of PSR by combining the individual PSRs of each analog block through the frequency dependent gain of the following blocks. Since bandgap reference generators, voltage to current generators, and voltage buffers are crucial blocks in analog systems, they are chosen to be the case of study to validate the theory developed in this work. With no loss of generality, the method can be applied to any chain of analog blocks under assumption of linear operation. The circuit used to explain the concept is implemented in 0.25-µm CMOS technology.