基于锁存器的门限逻辑门的紧凑延迟建模

M. Padure, S. Cotofana, C. Dan, S. Vassiliadis, M. Bodea
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引用次数: 1

摘要

本文提出了一种新的基于锁存器的CMOS阈值逻辑门的紧凑静态延迟模型。模型捕捉到的特殊效应是。延迟对阈值(数据)值的依赖性以及延迟与容性负载的依赖性。从几种门限逻辑门设置中提取了模型参数,计算机算法基本电路的模型预测延迟与电路仿真完全吻合。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Compact delay modeling of latch-based threshold logic gates
In this paper we propose a new compact static delay model for latch-based CMOS threshold logic gates. The particular effects captured by the model are. the dependency of the delay on threshold (data) values and the dependency of the delay vs. capacitive loading. The model parameters were extracted from several Threshold logic gate setups and the delay predicted by the model fora computer arithmetic basic circuit fully agree with circuit simulations.
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