Quantitative model of CMOS inverter chain ring oscillator's effective capacitance and its improvements in 14nm FinFET technology

The quantitative model of effective total capacitance, Ceff, of a CMOS ring oscillator (R/O) inverter chain in a 14nm node FinFET 3D structure using advanced Replacement Metal Gate (RMG) is successfully extracted using all the unit capacitance components comprising the R/O, such as inverter, fan-out (F/O) MOSCAP, and metal routing. The extracted Ceff model is well validated by perfect matching to the measured Si Ceff in the R/O. This paper provides a concise and clear Ceff quantitative model of inverter R/O chain using individual transistor capacitance components such as channel capacitance (Cgc), overlap capacitance (Cov), junction capacitance (Cj) and metal wire capacitance (Cwire) considering the R/O layout and its operation mechanism, which has never been reported before. Furthermore, Cov is decomposed with the gate to contact capacitance (Cmol), EPI source-drain (S/D) to gate on Fin top (Cft), EPI S/D to gate on Fin sidewall (Cfb) and intrinsic gate to S/D overlap capacitance (Cdo) with Si data and simulation. Contribution to Ceff by all the capacitor components from Cgc, Cmol, Cj, Cwire, Cft, Cfb and Cdo is extracted with Si validation. Cov reduction without DC performance degradation is also provided in this paper.