{"title":"高温下不同排水工程下UTBB SOI增强动态阈值运行的DIBL","authors":"K. Sasaki, E. Simoen, C. Claeys, J. Martino","doi":"10.1109/SBMICRO.2016.7731329","DOIUrl":null,"url":null,"abstract":"Focusing on the DIBL (Drain Induced Barrier Lowering), this paper investigates for the first time the influence of the overlap/underlap gate to drain engineering on UTBB SOI devices in conventional and enhanced dynamic threshold voltage operation at high temperatures. Although the temperature degrades this parameter, the best DIBL performance was obtained for the enhanced mode operation and longer underlap length.","PeriodicalId":113603,"journal":{"name":"2016 31st Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"DIBL in enhanced dynamic threshold operation of UTBB SOI with different drain engineering at high temperatures\",\"authors\":\"K. Sasaki, E. Simoen, C. Claeys, J. Martino\",\"doi\":\"10.1109/SBMICRO.2016.7731329\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Focusing on the DIBL (Drain Induced Barrier Lowering), this paper investigates for the first time the influence of the overlap/underlap gate to drain engineering on UTBB SOI devices in conventional and enhanced dynamic threshold voltage operation at high temperatures. Although the temperature degrades this parameter, the best DIBL performance was obtained for the enhanced mode operation and longer underlap length.\",\"PeriodicalId\":113603,\"journal\":{\"name\":\"2016 31st Symposium on Microelectronics Technology and Devices (SBMicro)\",\"volume\":\"90 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 31st Symposium on Microelectronics Technology and Devices (SBMicro)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SBMICRO.2016.7731329\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 31st Symposium on Microelectronics Technology and Devices (SBMicro)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBMICRO.2016.7731329","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
DIBL in enhanced dynamic threshold operation of UTBB SOI with different drain engineering at high temperatures
Focusing on the DIBL (Drain Induced Barrier Lowering), this paper investigates for the first time the influence of the overlap/underlap gate to drain engineering on UTBB SOI devices in conventional and enhanced dynamic threshold voltage operation at high temperatures. Although the temperature degrades this parameter, the best DIBL performance was obtained for the enhanced mode operation and longer underlap length.