一种用于集成电路的内禀区域阵列pad路由器

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI:10.1109/ASIC.1997.617018

C. Tan, D. Bouldin, P. Dehkordi

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引用次数: 10

摘要

在IC的核心电路上以矩阵阵列排列I/ o通常比将衬垫限制在外围的传统方法提供5-10倍的I/ o。这种方法也使整体模具尺寸最小化。在本文中，我们描述了一种新的区域阵列pad路由器的开发，它与其他方法的不同之处在于，它不需要添加额外的金属层(除非需要)，也不需要重新分配。我们描述了该技术的设计实现，并展示了将该路由器应用于需要112、298、414和485个I/ o的设计的结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An intrinsic area-array pad router for ICs

Arranging I/Os in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/Os than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design implementation of this technique and show the results of applying this router on designs requiring 112, 298, 414 and 485 I/Os.

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来源期刊

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

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