面向未来超高密度DRAM的新型三维(3D)存储器阵列架构

2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI:10.1109/ICMEL.2000.838729

T. Endoh, H. Sakuraba, Katsuhisa Shinmei, F. Masuoka

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引用次数: 6

摘要

三维存储阵列结构是通过在二维阵列矩阵中的每个单元上垂直堆叠多个单元来实现的。当一个位线有1个k位单元且使用相同的设计规则时，该架构的DRAM的总位线电容被抑制到普通DRAM的37%。此外，使用该架构的1m位DRAM的阵列面积减少到使用相同设计规则的普通DRAM的11.5%。

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New three dimensional (3D) memory array architecture for future ultra high density DRAM

A three dimensional (3D) memory array architecture is realized by stacking several cells in series vertically up on each cell which is located in two dimensional (2D) array matrix. Total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM, when one bit-line has 1 K-bit cells and the same design rules are used. Moreover, array area of 1 M-bit DRAM using the proposed architecture, is reduced to 11.5% of normal DRAM using the same design rules.

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来源期刊

2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)

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