Energy Efficiency of Microring Resonator (MRR)-Based Binary Decision Diagram (BDD) Circuits

The saturation of rapid progress in transistor technology has brought us to a point where the computing systems face fundamental physical limitations. Emerging technologies propose various alternatives and photonic circuits are among promising candidates due to their high operation speed, energy efficient passive components, low crosstalk and appropriateness for parallel computation. In this work, we design a microring resonator (MRR) based Binary Decision Diagram (BDD) NAND logic gate and study its characteristics inline with a MRR-based BDD half adder circuit proposed by Wada et. al. [1]. We analyze energy efficiency limitations of BDD architectures using reversible and irreversible circuit structures. The circuits we focus on in this work are composed of silicon MRR-based switching nodes where the coupling gap and ring size play a key role in the performance of the circuits. We study the physical structure of the circuits as well as dynamics of the information processing, and calculate the fundamental lower bounds on the energy dissipation as a result of computation. We also perform extensive analyses on Lumerical MODE simulations to optimize the energy efficiency based on various factors including waveguide properties, ring radius and gap size. The results we obtain allow us to assess limitations imposed by the physical nature of MRR-based photonic circuits in computation, and compare theory against simulation and hence significantly contribute to the strategic development of this technology as a part of future computers.