Debug and diagnosis in the age of system-on-a-chip

The current scale of integration is the greatest driving force for needing better and faster, debug capabilities. We are truly building systems on a chip, board level interfaces which could previously be monitored and debugged with logic analyzers are now buried on silicon. We need to consider burying the logic analyzers along with the interfaces. The debug task is sometimes made more difficult in today’s environment with the increased reuse of internal IP, the use of externally supplied IP and remote foundries. Internal reuse of IP may not at first seem like a complicating factor but consider the likely fact that few if any of the original designers of that block are still with the company and you are intending to use it in a design that they had not even thought of. With increased IP reuse our marketing folks, in their infinite wisdom, are tempted to offer more parts in the market, many just a small customization of the base model. “Hey just cut the cache in half, slap on a 10/100 IP block from TI, cut the cost by 30% and we’ve opened up a whole new market!” Right! We are not plug and play in the microprocessor component domain yet. We are executing these design customizations but at this time the extended debug phase may more than compensate for the design time saved due to IP purchase or reuse.