TSV的紧凑建模与仿真，并进行了实验验证

2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2016-04-25 DOI:10.1109/VLSI-TSA.2016.7480488

Jhih-Yang Yan, Sun-Rong Jan, Yi-Chung Huang, H. Lan, C. W. Liu, Y.-H. Huang, B. Hung, K.T. Chan, Michael Huang, M. Yang

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引用次数: 1

摘要

研究了最后通硅通孔(TSV)对28nm节点器件的影响。TSV的应力场受后端介质(BEOL)的影响。硅表面的径向应力绝对值(|σr|)与切向应力绝对值(|σθ|)不同，导致不对称保持区(KOZ)的形成。本文还描述了不对称背后的物理原理。提出了一种考虑非对称应力场的修正KOZ模型，并用实验数据进行了验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Compact modeling and simulation of TSV with experimental verification

Impact of via-last through-silicon via (TSV) on 28nm node devices is investigated. The stress field of TSV is affected by the back-end-of-line (BEOL) dielectrics. The absolute value of radial stress (|σr|) is different from that of tangential stress (|σθ|) on silicon, which leads to the asymmetric keep-out zone (KOZ). The physics behind the asymmetry is also described. A modified KOZ model considering the asymmetric stress field is proposed and verified by experiment data.

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2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

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