{"title":"采用PWM/PFM模式的高效低功耗DC-DC变换器的设计与实现","authors":"Jing Wang, Wenchao Gong, Lenian He","doi":"10.1109/ICASIC.2007.4415701","DOIUrl":null,"url":null,"abstract":"A high-efficiency low-power multimode DC-DC converter with pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is proposed. This converter works in PWM mode on heavy load condition. In order to improve efficiency, it switches to PFM mode on light load condition. With suitable control and mode switch method, both simulation and chip test results indicate that the converter performs seamless switching between PWM and PFM modes. The total output voltage error, including line and load regulation, is less than plusmn2%, the maximum quiescent current is less than 15 muA, the maximum of efficiency reaches 92.6%. Simulated and implemented in CSMC 0.5 mum CMOS process.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Design and implementation of high-efficiency and low-power DC-DC converter with PWM/PFM modes\",\"authors\":\"Jing Wang, Wenchao Gong, Lenian He\",\"doi\":\"10.1109/ICASIC.2007.4415701\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high-efficiency low-power multimode DC-DC converter with pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is proposed. This converter works in PWM mode on heavy load condition. In order to improve efficiency, it switches to PFM mode on light load condition. With suitable control and mode switch method, both simulation and chip test results indicate that the converter performs seamless switching between PWM and PFM modes. The total output voltage error, including line and load regulation, is less than plusmn2%, the maximum quiescent current is less than 15 muA, the maximum of efficiency reaches 92.6%. Simulated and implemented in CSMC 0.5 mum CMOS process.\",\"PeriodicalId\":120984,\"journal\":{\"name\":\"2007 7th International Conference on ASIC\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 7th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2007.4415701\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415701","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
摘要
提出了一种具有脉宽调制(PWM)和脉频调制(PFM)的高效低功耗多模DC-DC变换器。该变换器在重载条件下工作在PWM模式下。为了提高效率，它在轻载状态下切换到PFM模式。通过适当的控制和模式切换方法，仿真和芯片测试结果表明，该变换器可以在PWM和PFM模式之间无缝切换。包括线路和负载调节在内的总输出电压误差小于±2%，最大静态电流小于15 muA，最高效率达到92.6%。在CSMC 0.5 μ m CMOS工艺中进行了仿真和实现。
Design and implementation of high-efficiency and low-power DC-DC converter with PWM/PFM modes
A high-efficiency low-power multimode DC-DC converter with pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is proposed. This converter works in PWM mode on heavy load condition. In order to improve efficiency, it switches to PFM mode on light load condition. With suitable control and mode switch method, both simulation and chip test results indicate that the converter performs seamless switching between PWM and PFM modes. The total output voltage error, including line and load regulation, is less than plusmn2%, the maximum quiescent current is less than 15 muA, the maximum of efficiency reaches 92.6%. Simulated and implemented in CSMC 0.5 mum CMOS process.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
