A Run-Time Library for Parallel Processing on a Multi-core DSP

Future of the computer based systems resides in the multi-core and many-core architectures. Thanks to availability of different multi-core processors, many parallelization tools and techniques emerged. However, majority of them rely on the shared memory architecture model, where data to multiple core processors is simply accessible. In this paper we present a simple hardware abstraction that targets features of a multi-core DSP processor with distributed memory architecture, aiming support for program parallelization. Both manual and automatic code parallelization approaches can use library routines described in this paper. By validating performance of multiple manually created test cases we demonstrate capabilities of presented approach. Performance is estimated by measuring time necessary for DMA data transfer between the cores using GPIO pins attached to the DSP. In addition, earlier developed C code parallelization technique for the same DSP is extended to use this library providing full working solution verified on real hardware.