CMOS V-I converter with 75dB SFDR and 360/spl mu/W power consumption

This work describes a new circuit solution for a linear, CMOS voltage-to-current converter (V-I converter or transconductor). The circuit utilizes a combination of cross-coupling and local resistive feedback for a significant, simultaneous suppression of the third and the fifth order harmonic distortion components in the transconductor characteristics. The transistor implementation is presented and a prototype VI converter is realised in a digital 0.18 /spl mu/m CMOS technology. The measured SFDR is 75 dB in a frequency band of 10 MHz. The circuit occupies 0.02 mm/sup 2/ and dissipates 360 /spl mu/W.