fpga上全局同步局部异步系统的体系结构

D. L. Oliveira, L. Faria, Higor A. Delsoto, Kledermon Garcia
{"title":"fpga上全局同步局部异步系统的体系结构","authors":"D. L. Oliveira, L. Faria, Higor A. Delsoto, Kledermon Garcia","doi":"10.1109/INTERCON.2016.7815572","DOIUrl":null,"url":null,"abstract":"Taking advantage of synchronous and asynchronous paradigms, a new style of design called Globally Synchronous Locally Asynchronous (GSLA) has achieved very interesting results. In this paper, we propose a high-performance interface that allows the communication of synchronous to asynchronous to synchronous modules. Internally, the proposed interface comprises an asynchronous module. The GSLA design style is the most suitable one for FPGA (Field-Programmable Gate Array) platforms, because it facilitates the SoC (Systems–on-Chip) design. Through a case study, the “differential equation solver”, we show that the proposed interface presents a reduction of 33% in the processing time when compared with a synchronous design. The proposed interface lets you interact with other synchronous modules in a frequency up to 500 MHz.","PeriodicalId":244277,"journal":{"name":"2016 IEEE XXIII International Congress on Electronics, Electrical Engineering and Computing (INTERCON)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An architecture for globally-synchronous locally-asynchronous systems on FPGAs\",\"authors\":\"D. L. Oliveira, L. Faria, Higor A. Delsoto, Kledermon Garcia\",\"doi\":\"10.1109/INTERCON.2016.7815572\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Taking advantage of synchronous and asynchronous paradigms, a new style of design called Globally Synchronous Locally Asynchronous (GSLA) has achieved very interesting results. In this paper, we propose a high-performance interface that allows the communication of synchronous to asynchronous to synchronous modules. Internally, the proposed interface comprises an asynchronous module. The GSLA design style is the most suitable one for FPGA (Field-Programmable Gate Array) platforms, because it facilitates the SoC (Systems–on-Chip) design. Through a case study, the “differential equation solver”, we show that the proposed interface presents a reduction of 33% in the processing time when compared with a synchronous design. The proposed interface lets you interact with other synchronous modules in a frequency up to 500 MHz.\",\"PeriodicalId\":244277,\"journal\":{\"name\":\"2016 IEEE XXIII International Congress on Electronics, Electrical Engineering and Computing (INTERCON)\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE XXIII International Congress on Electronics, Electrical Engineering and Computing (INTERCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/INTERCON.2016.7815572\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE XXIII International Congress on Electronics, Electrical Engineering and Computing (INTERCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INTERCON.2016.7815572","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

利用同步和异步范例,一种称为全局同步局部异步(GSLA)的新设计风格取得了非常有趣的结果。在本文中,我们提出了一个高性能接口,允许同步到异步到同步模块的通信。在内部,建议的接口包含一个异步模块。GSLA设计风格是最适合FPGA(现场可编程门阵列)平台的设计风格,因为它有利于SoC(片上系统)设计。通过一个案例研究,“微分方程求解器”,我们表明,与同步设计相比,所提出的接口在处理时间上减少了33%。所提出的接口允许您以高达500 MHz的频率与其他同步模块进行交互。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An architecture for globally-synchronous locally-asynchronous systems on FPGAs
Taking advantage of synchronous and asynchronous paradigms, a new style of design called Globally Synchronous Locally Asynchronous (GSLA) has achieved very interesting results. In this paper, we propose a high-performance interface that allows the communication of synchronous to asynchronous to synchronous modules. Internally, the proposed interface comprises an asynchronous module. The GSLA design style is the most suitable one for FPGA (Field-Programmable Gate Array) platforms, because it facilitates the SoC (Systems–on-Chip) design. Through a case study, the “differential equation solver”, we show that the proposed interface presents a reduction of 33% in the processing time when compared with a synchronous design. The proposed interface lets you interact with other synchronous modules in a frequency up to 500 MHz.
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