Impacts of Nested Variance Components on Semiconductor Electrical Test Sampling

Inline wafer electrical testing (WET) offers an early read on semiconductor manufacturing processes via measurements taken on test structures placed throughout the wafer. Interpreting the data can be challenging, however. In many cases, only a sample of the test sites are monitored in production. Complex manufacturing requirements further complicate the problem because some operations are iteratively executed within subregions across a given wafer, while others are run on the entire wafer at once, and still others are applied to wafers in batches. This results in a nested variance structure under which different physical mechanisms exhibit varying sensitivities to site-to-site, wafer-to-wafer, and lot-to-lot variations. This article uses Monte Carlo simulations to explore the impacts these hierarchical variance components can exert on perceptions of WET performance.