Co-evaluation of FPGA architectures and the CAD system for telecommunication

We propose an FPGA architecture for next generation B-ISDN telecommunications systems. Such a system requires an FPGA in which an over 10 K gates circuit can be implemented and that has a clock cycle rate of 80 MHz. While the FPGA architecture has been discussed in terms of its circuit structure, we consider the circuit structure of the FPGA with its CAD tools. We evaluate several FPGA logic-element structures with a technology mapping method. From our experiments, the multiplexer based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method.