{"title":"利用多故障传播加速故障模拟","authors":"Y. Xing, G. van Brakel, H. Kerkhoff","doi":"10.1109/ATS.1992.224432","DOIUrl":null,"url":null,"abstract":"An efficient parallel pattern multiple-fault propagation (MFP) technique for the single stuck-at fault simulation in combinational circuits is presented. This technique is able to operate in conjunction with several existing fault simulation techniques, such as the parallel-pattern simulation and the fanout-free region concept. Experimental results have shown significant improvements in the simulation speed over the existing approaches. The fault simulator described adopts different simulation algorithms at different simulation stages to optimize the simulator performance.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Accelerated fault simulation utilizing multiple-fault propagation\",\"authors\":\"Y. Xing, G. van Brakel, H. Kerkhoff\",\"doi\":\"10.1109/ATS.1992.224432\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An efficient parallel pattern multiple-fault propagation (MFP) technique for the single stuck-at fault simulation in combinational circuits is presented. This technique is able to operate in conjunction with several existing fault simulation techniques, such as the parallel-pattern simulation and the fanout-free region concept. Experimental results have shown significant improvements in the simulation speed over the existing approaches. The fault simulator described adopts different simulation algorithms at different simulation stages to optimize the simulator performance.<<ETX>>\",\"PeriodicalId\":208029,\"journal\":{\"name\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-11-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1992.224432\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings First Asian Test Symposium (ATS `92)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1992.224432","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An efficient parallel pattern multiple-fault propagation (MFP) technique for the single stuck-at fault simulation in combinational circuits is presented. This technique is able to operate in conjunction with several existing fault simulation techniques, such as the parallel-pattern simulation and the fanout-free region concept. Experimental results have shown significant improvements in the simulation speed over the existing approaches. The fault simulator described adopts different simulation algorithms at different simulation stages to optimize the simulator performance.<>
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