40gbit /s集成电路的InP HBT自对准技术:制备及CAD几何模型

Conference Proceedings. Eleventh International Conference on Indium Phosphide and Related Materials (IPRM'99) (Cat. No.99CH36362) Pub Date : 1999-05-16 DOI:10.1109/ICIPRM.1999.773738

S. Blayac, M. Riet, J. Benchimol, M. Abboun, F. Aniel, P. Berdaguer, A.M. Duchenois, A. Konczykowska, J. Godin

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引用次数: 8

摘要

首次提出了用于40gb /s集成电路的InP/InGaAs DHBT技术。对于这些电路应用，需要足够的击穿电压(>5 V)，静态增益约50，截止频率(f/sub T/)和最大振荡频率(f/sub max/)大于100 GHz。利用化学束外延(CBE)生长的高性能InP/InGaAs DHBT在电流密度为1/ sp1倍/10/sup 5/ a /cm/sup 2/的情况下，具有125 GHz f/sub T/， 128 GHz f/sub max/和50的增益。器件几何优化是使用基于一组解析方程的几何模型来执行的。该工具不仅可以实现技术优化，还可以根据电路中器件的尺寸进行功能调整。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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InP HBT self-aligned technology for 40 Gbit/s ICs: fabrication and CAD geometric model

InP/InGaAs DHBT technology for 40 Gb/s ICs is first presented. For these circuit applications, a sufficient breakdown voltage (>5 V), a static gain around 50, cutoff frequencies (f/sub T/) and maximum oscillation frequencies (f/sub max/) greater than 100 GHz are needed. High performance InP/InGaAs DHBT grown by chemical beam epitaxy (CBE) are reported with 125 GHz f/sub T/, 128 GHz f/sub max/ and a gain of 50 at a current density of 1/spl times/10/sup 5/ A/cm/sup 2/. Devices geometry optimisation is performed using a geometric model based on a set of analytical equations. This tool allows not only technological optimisation but also function-adapted individual sizing of the devices in the circuits.

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Conference Proceedings. Eleventh International Conference on Indium Phosphide and Related Materials (IPRM'99) (Cat. No.99CH36362)

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