ATREX:设计用于Mega Gate lsi的可测试系统

Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI:10.1109/ATS.1997.643947

Michiaki Emori, Junko Kumagai, Koichi Itaya, T. Aikyo, Tomoko Anan, Junichi Niimi

{"title":"ATREX:设计用于Mega Gate lsi的可测试系统","authors":"Michiaki Emori, Junko Kumagai, Koichi Itaya, T. Aikyo, Tomoko Anan, Junichi Niimi","doi":"10.1109/ATS.1997.643947","DOIUrl":null,"url":null,"abstract":"We propose a Design for Testability System for Mega Gate LSIs. This system meets various demands of designers, because this system has high flexibility. We show the flexibility by introducing some examples of circuit insertion which is supported by the system.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"ATREX: Design for testability system for Mega Gate LSIs\",\"authors\":\"Michiaki Emori, Junko Kumagai, Koichi Itaya, T. Aikyo, Tomoko Anan, Junichi Niimi\",\"doi\":\"10.1109/ATS.1997.643947\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a Design for Testability System for Mega Gate LSIs. This system meets various demands of designers, because this system has high flexibility. We show the flexibility by introducing some examples of circuit insertion which is supported by the system.\",\"PeriodicalId\":330767,\"journal\":{\"name\":\"Proceedings Sixth Asian Test Symposium (ATS'97)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Sixth Asian Test Symposium (ATS'97)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1997.643947\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Sixth Asian Test Symposium (ATS'97)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1997.643947","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

我们提出了一种megagate lsi的可测试性系统设计。该系统具有很高的灵活性，满足了设计人员的各种需求。通过介绍系统支持的一些电路插入实例，说明了系统的灵活性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

ATREX: Design for testability system for Mega Gate LSIs

We propose a Design for Testability System for Mega Gate LSIs. This system meets various demands of designers, because this system has high flexibility. We show the flexibility by introducing some examples of circuit insertion which is supported by the system.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings Sixth Asian Test Symposium (ATS'97)

自引率

0.00%

发文量