Han-Su Kim, Chulho Chung, Joohyun Jeong, Seung-Jae Jung, Jinsung Lim, J. Joe, Jaehoon Park, Hyunwoo Lee, G. Jo, Kangwook Park, Jedon D. Kim, Hansu Oh, J. Yoon
{"title":"工艺尺度对标准CMOS工艺制造晶体管射频性能的影响","authors":"Han-Su Kim, Chulho Chung, Joohyun Jeong, Seung-Jae Jung, Jinsung Lim, J. Joe, Jaehoon Park, Hyunwoo Lee, G. Jo, Kangwook Park, Jedon D. Kim, Hansu Oh, J. Yoon","doi":"10.1109/RFIC.2008.4561498","DOIUrl":null,"url":null,"abstract":"Cut-off frequency (f<sub>T</sub>) of 300 GHz and 230 GHz for NMOS and PMOS is demonstrated for transistors with a gate length of 35 nm fabricated by 45 nm standard CMOS technology. Current gain (H<sub>21</sub>) and noise (flicker and thermal) is improved with scaling down technology. Power gain (G<sub>u</sub>) increase is slow down and even saturated at 45 nm as technology advances. Such saturation in power gain is attributed to rapid increase in g<sub>ds</sub> (drain conductance). Additional efforts are required to reduce g<sub>ds</sub> for continuous improvement in power gain with the scaling. V<sub>th</sub> optimization can be one of options to achieve better g<sub>ds</sub>.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"164 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Effect of technology scaling on RF performance of the transistors fabricated by standard CMOS technology\",\"authors\":\"Han-Su Kim, Chulho Chung, Joohyun Jeong, Seung-Jae Jung, Jinsung Lim, J. Joe, Jaehoon Park, Hyunwoo Lee, G. Jo, Kangwook Park, Jedon D. Kim, Hansu Oh, J. Yoon\",\"doi\":\"10.1109/RFIC.2008.4561498\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Cut-off frequency (f<sub>T</sub>) of 300 GHz and 230 GHz for NMOS and PMOS is demonstrated for transistors with a gate length of 35 nm fabricated by 45 nm standard CMOS technology. Current gain (H<sub>21</sub>) and noise (flicker and thermal) is improved with scaling down technology. Power gain (G<sub>u</sub>) increase is slow down and even saturated at 45 nm as technology advances. Such saturation in power gain is attributed to rapid increase in g<sub>ds</sub> (drain conductance). Additional efforts are required to reduce g<sub>ds</sub> for continuous improvement in power gain with the scaling. V<sub>th</sub> optimization can be one of options to achieve better g<sub>ds</sub>.\",\"PeriodicalId\":253375,\"journal\":{\"name\":\"2008 IEEE Radio Frequency Integrated Circuits Symposium\",\"volume\":\"164 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Radio Frequency Integrated Circuits Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2008.4561498\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Radio Frequency Integrated Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2008.4561498","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effect of technology scaling on RF performance of the transistors fabricated by standard CMOS technology
Cut-off frequency (fT) of 300 GHz and 230 GHz for NMOS and PMOS is demonstrated for transistors with a gate length of 35 nm fabricated by 45 nm standard CMOS technology. Current gain (H21) and noise (flicker and thermal) is improved with scaling down technology. Power gain (Gu) increase is slow down and even saturated at 45 nm as technology advances. Such saturation in power gain is attributed to rapid increase in gds (drain conductance). Additional efforts are required to reduce gds for continuous improvement in power gain with the scaling. Vth optimization can be one of options to achieve better gds.
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