{"title":"2.5 gb/s GaAs ATM Mux Demux ASIC","authors":"J. K. Madsen, P. Lassen","doi":"10.1109/GAAS.1995.528957","DOIUrl":null,"url":null,"abstract":"This paper describes the design and implementation of a high speed GaAs ATM Mux Demur ASIC (AMDA) which is the key element in a high speed ATM Add-Drop unit. This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The Add-Drop unit provides a cell based interface between networks/systems operating at different data rates, the high speed interface being 2.5 Gb/s and the low speed interface being 155/622 Mb/s. Self-timed FIFOs are used for handling the speed gaps between domains operating at different clock rates, and a Self-Timed At Receiver's Input (STARI) interface is used at all high speed chip-to-chip links to eliminate timing skews The AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 2.5 gb/s GaAs ATM Mux Demux ASIC\",\"authors\":\"J. K. Madsen, P. Lassen\",\"doi\":\"10.1109/GAAS.1995.528957\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design and implementation of a high speed GaAs ATM Mux Demur ASIC (AMDA) which is the key element in a high speed ATM Add-Drop unit. This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The Add-Drop unit provides a cell based interface between networks/systems operating at different data rates, the high speed interface being 2.5 Gb/s and the low speed interface being 155/622 Mb/s. Self-timed FIFOs are used for handling the speed gaps between domains operating at different clock rates, and a Self-Timed At Receiver's Input (STARI) interface is used at all high speed chip-to-chip links to eliminate timing skews The AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W.\",\"PeriodicalId\":422183,\"journal\":{\"name\":\"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1995.528957\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1995.528957","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes the design and implementation of a high speed GaAs ATM Mux Demur ASIC (AMDA) which is the key element in a high speed ATM Add-Drop unit. This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The Add-Drop unit provides a cell based interface between networks/systems operating at different data rates, the high speed interface being 2.5 Gb/s and the low speed interface being 155/622 Mb/s. Self-timed FIFOs are used for handling the speed gaps between domains operating at different clock rates, and a Self-Timed At Receiver's Input (STARI) interface is used at all high speed chip-to-chip links to eliminate timing skews The AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W.