A 5.5-V 7-MHz UGBW Dual Rail-to-Rail CMOS Op Amp with Enable Pin and Hi-Z Output Feature

The paper presents a dual rail-to-rail CMOS op amp having a unity-gain bandwidth (UGBW) better than 7 MHz across the 2.5-5.5 V supply range. The circuit has an Enable pin and, during Disable status, its outputs are in Hi-Z, avoiding current flowing into circuit from the load that is prone to get higher than the supply voltage. It was fabricated using a $0.25 {\mu} \mathrm{m}$ BCD process. The amplifier has a maximum offset voltage of 1 mV, a minimum PSRR of 95 dB, a minimum CMRR of 66 dB, a minimum open-loop gain of 100 dB, and a voltage noise spectral density of 20 nV/$\surd$Hz at 10 kHz, while consuming $850 {\mu} \mathrm{A}$ per channel. The die area is only 1 mm2 and has no package, but 9 bumps.