绝缘子(III-V-O-I)上的超薄体自对准InGaAs mosfet

Jianqiang Lin, L. Czornomaz, N. Daix, D. Antoniadis, J. D. del Alamo
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引用次数: 5

摘要

本文报道了一种在III-V-O-I衬底上采用紧密节距工艺制备的自对准InGaAs量子阱MOSFET (QW-MOSFET)。采用直接键合技术在Si上制备了超薄体(UTB) III-V-O-I层结构。采用栅末法制备了具有自对准栅极和金属触点的III-V型mosfet。我们首次展示了接触金属间距为150nm的相邻器件。该制造具有CMOS兼容性,前端无湿蚀,无升降和无au工艺。研究了输运和短通道效应(SCE)作为背偏压的函数。通过DIBL和亚阈值摆动,以最新的III-V-O-I数据为基准,获得了出色的SCE控制。该技术为未来高密度电路应用提供了集成III-V前端器件的新途径。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Ultra-thin-body self-aligned InGaAs MOSFETs on insulator (III-V-O-I) by a tight-pitch process
We report a self-aligned InGaAs Quantum-Well MOSFET (QW-MOSFET) on III-V-O-I substrate fabricated through a tight-pitch process. The ultra-thin body (UTB) III-V-O-I layer structure was fabricated on Si through a direct bonding technique. The III-V MOSFETs, with a self-aligned gate and metal contacts, were fabricated by a gate-last method. For the first time, we demonstrate adjacent devices with contact metal spacing of 150 nm. The fabrication features CMOS compatibility with a wet-etch free, lift-off free and Au-free process in the front end. Transport and short-channel effects (SCE) are studied as a function of back bias. Excellent SCE control is obtained with DIBL and subthreshold swing benchmarked against state-of-the-art III-V-O-I data. The reported technology provides a new path to integrate III-V front-end devices for future high density circuit applications.
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