N. Wrachien, A. Cester, Nicolò Lago, G. Meneghesso, R. D'Alpaos, A. Stefani, G. Turatti, M. Muccini
{"title":"恒压应力对有机互补逻辑逆变器的影响","authors":"N. Wrachien, A. Cester, Nicolò Lago, G. Meneghesso, R. D'Alpaos, A. Stefani, G. Turatti, M. Muccini","doi":"10.1109/ESSDERC.2014.6948819","DOIUrl":null,"url":null,"abstract":"We subjected all-organic complementary inverters to constant voltage stress. We found a 20% maximum variation of DC inverter parameters after a 104-s stress. The largest degradation was in the delay times, which increase up to a factor 7. This is due to the threshold voltage variation in pTFTs and the mobility reduction in nTFTs.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Effects of constant voltage stress on organic complementary logic inverters\",\"authors\":\"N. Wrachien, A. Cester, Nicolò Lago, G. Meneghesso, R. D'Alpaos, A. Stefani, G. Turatti, M. Muccini\",\"doi\":\"10.1109/ESSDERC.2014.6948819\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We subjected all-organic complementary inverters to constant voltage stress. We found a 20% maximum variation of DC inverter parameters after a 104-s stress. The largest degradation was in the delay times, which increase up to a factor 7. This is due to the threshold voltage variation in pTFTs and the mobility reduction in nTFTs.\",\"PeriodicalId\":262652,\"journal\":{\"name\":\"2014 44th European Solid State Device Research Conference (ESSDERC)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 44th European Solid State Device Research Conference (ESSDERC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2014.6948819\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 44th European Solid State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2014.6948819","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effects of constant voltage stress on organic complementary logic inverters
We subjected all-organic complementary inverters to constant voltage stress. We found a 20% maximum variation of DC inverter parameters after a 104-s stress. The largest degradation was in the delay times, which increase up to a factor 7. This is due to the threshold voltage variation in pTFTs and the mobility reduction in nTFTs.