{"title":"面向arm系列处理器的低成本高性能流水线代码解压缩引擎","authors":"Y. Jeang, Ko-Yen Hu","doi":"10.1109/ICICIC.2009.25","DOIUrl":null,"url":null,"abstract":"Several techniques have been presented in our previous work for lessening the delays for instruction decompression when branching occurs. However, their costs are still relatively high. In this paper, a new preprocessing-based technique is presented to reduce the cost and increase the performance. The synthesized results for several benchmarks show that the average saving of area is about 37.5%.","PeriodicalId":240226,"journal":{"name":"2009 Fourth International Conference on Innovative Computing, Information and Control (ICICIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Low-Cost and High Performance Pipelined Code Decompression Engine for ARM-Series Processors\",\"authors\":\"Y. Jeang, Ko-Yen Hu\",\"doi\":\"10.1109/ICICIC.2009.25\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Several techniques have been presented in our previous work for lessening the delays for instruction decompression when branching occurs. However, their costs are still relatively high. In this paper, a new preprocessing-based technique is presented to reduce the cost and increase the performance. The synthesized results for several benchmarks show that the average saving of area is about 37.5%.\",\"PeriodicalId\":240226,\"journal\":{\"name\":\"2009 Fourth International Conference on Innovative Computing, Information and Control (ICICIC)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Fourth International Conference on Innovative Computing, Information and Control (ICICIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICIC.2009.25\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Fourth International Conference on Innovative Computing, Information and Control (ICICIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICIC.2009.25","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Low-Cost and High Performance Pipelined Code Decompression Engine for ARM-Series Processors
Several techniques have been presented in our previous work for lessening the delays for instruction decompression when branching occurs. However, their costs are still relatively high. In this paper, a new preprocessing-based technique is presented to reduce the cost and increase the performance. The synthesized results for several benchmarks show that the average saving of area is about 37.5%.