TRIPS原型芯片的设计与实现

2005 IEEE Hot Chips XVII Symposium (HCS) Pub Date : 2005-08-01 DOI:10.1109/HOTCHIPS.2005.7476592

Robert G. McDonald, D. Burger, S. Keckler

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引用次数: 7

摘要

本文由作者在会议上演讲的幻灯片集合组成。他们的结论是:分布式微架构承认并容忍为分布式组件定制的线延迟和可扩展协议。平铺微架构简化了可伸缩性，提高了设计效率。指令级并行的下一步是EDGE ISA，它可以提高ILP，同时还可以利用更粗略的并行类型。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The design and implementation of the TRIPS prototype chip

This article consists of a collection of slides from the authors' conference presentation. They conclude that: distributed microarchitecture acknowledges and tolerates wire delay and scalable protocols tailored for distributed components. Tiled microarchitecture simplifies scalability and improves design productivity. The next step for instruction-level parallelism is EDGE ISA enables increased ILP while also exploiting coarser types of parallelism.

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2005 IEEE Hot Chips XVII Symposium (HCS)

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