Eugene Koskin, P. Bisiaux, D. Galayko, E. Blokhina
{"title":"事件驱动ADPLL的FPGA验证","authors":"Eugene Koskin, P. Bisiaux, D. Galayko, E. Blokhina","doi":"10.1109/ECCTD49232.2020.9218367","DOIUrl":null,"url":null,"abstract":"In this paper, we perform FPGA modeling of an event-driven all-digital phase locked loop (ADPLL) with asynchronous control. We perform the comparison with a theoretical model through a transient response, phase plane representation, and the order parameter. The hardware simulations showed a very good agreement with the theoretical model, which can be used for studying more complex ADPLL networks.","PeriodicalId":336302,"journal":{"name":"2020 European Conference on Circuit Theory and Design (ECCTD)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"FPGA Validation of Event-Driven ADPLL\",\"authors\":\"Eugene Koskin, P. Bisiaux, D. Galayko, E. Blokhina\",\"doi\":\"10.1109/ECCTD49232.2020.9218367\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we perform FPGA modeling of an event-driven all-digital phase locked loop (ADPLL) with asynchronous control. We perform the comparison with a theoretical model through a transient response, phase plane representation, and the order parameter. The hardware simulations showed a very good agreement with the theoretical model, which can be used for studying more complex ADPLL networks.\",\"PeriodicalId\":336302,\"journal\":{\"name\":\"2020 European Conference on Circuit Theory and Design (ECCTD)\",\"volume\":\"81 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 European Conference on Circuit Theory and Design (ECCTD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECCTD49232.2020.9218367\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 European Conference on Circuit Theory and Design (ECCTD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD49232.2020.9218367","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we perform FPGA modeling of an event-driven all-digital phase locked loop (ADPLL) with asynchronous control. We perform the comparison with a theoretical model through a transient response, phase plane representation, and the order parameter. The hardware simulations showed a very good agreement with the theoretical model, which can be used for studying more complex ADPLL networks.