基于ITE专有CMOS工艺的院校MPW服务开发

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI:10.1109/MIXDES.2007.4286122

D. Obrbski, K. Kucharski, M. Grodner, A. Kokoszka, A. Malinowski, J. Lesiński, D. Tomaszewski, J. Malesinska

{"title":"基于ITE专有CMOS工艺的院校MPW服务开发","authors":"D. Obrbski, K. Kucharski, M. Grodner, A. Kokoszka, A. Malinowski, J. Lesiński, D. Tomaszewski, J. Malesinska","doi":"10.1109/MIXDES.2007.4286122","DOIUrl":null,"url":null,"abstract":"A MPW service has been arranged in the ITE in order to offer facility to academies for prototyping of CMOS ICs. This service is based on the proprietary CMOS process. The technology has been characterized via electrical measurements of dedicated test structures. The characteristics have been implemented in the form of design kit. Cadence reg design system has been chosen as a target tool for ICs design because of its popularity in European academies due to availability via EUROPRACTICE program. A number of functionalities have been implemented in the design kit. Namely, layout verification procedures (DRC, extraction, LVS) for Diva (TM) and Assura (TM) applications, automated generation of auxiliary technological layers (using Assura), layout import / export (GDSII, CIF formats) and corner analysis. Hence, a complete tool for ASICs design at the universities has been established.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"10 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Development of MPW Service for Academies Based on ITE Proprietary CMOS Process\",\"authors\":\"D. Obrbski, K. Kucharski, M. Grodner, A. Kokoszka, A. Malinowski, J. Lesiński, D. Tomaszewski, J. Malesinska\",\"doi\":\"10.1109/MIXDES.2007.4286122\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A MPW service has been arranged in the ITE in order to offer facility to academies for prototyping of CMOS ICs. This service is based on the proprietary CMOS process. The technology has been characterized via electrical measurements of dedicated test structures. The characteristics have been implemented in the form of design kit. Cadence reg design system has been chosen as a target tool for ICs design because of its popularity in European academies due to availability via EUROPRACTICE program. A number of functionalities have been implemented in the design kit. Namely, layout verification procedures (DRC, extraction, LVS) for Diva (TM) and Assura (TM) applications, automated generation of auxiliary technological layers (using Assura), layout import / export (GDSII, CIF formats) and corner analysis. Hence, a complete tool for ASICs design at the universities has been established.\",\"PeriodicalId\":310187,\"journal\":{\"name\":\"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems\",\"volume\":\"10 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIXDES.2007.4286122\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2007.4286122","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

为了为各学院提供CMOS集成电路原型设计的设施，在ITE中安排了MPW服务。该服务基于专有的CMOS工艺。该技术已通过专用测试结构的电气测量进行了表征。这些特性以设计工具包的形式实现。Cadence注册设计系统被选为集成电路设计的目标工具，因为它在欧洲学院的流行，因为可以通过EUROPRACTICE计划获得。设计套件中已经实现了许多功能。即Diva (TM)和Assura (TM)应用程序的布局验证程序(DRC，提取，LVS)，辅助技术层的自动生成(使用Assura)，布局导入/导出(GDSII, CIF格式)和角落分析。因此，建立了一个完整的大学专用集成电路设计工具。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Development of MPW Service for Academies Based on ITE Proprietary CMOS Process

A MPW service has been arranged in the ITE in order to offer facility to academies for prototyping of CMOS ICs. This service is based on the proprietary CMOS process. The technology has been characterized via electrical measurements of dedicated test structures. The characteristics have been implemented in the form of design kit. Cadence reg design system has been chosen as a target tool for ICs design because of its popularity in European academies due to availability via EUROPRACTICE program. A number of functionalities have been implemented in the design kit. Namely, layout verification procedures (DRC, extraction, LVS) for Diva (TM) and Assura (TM) applications, automated generation of auxiliary technological layers (using Assura), layout import / export (GDSII, CIF formats) and corner analysis. Hence, a complete tool for ASICs design at the universities has been established.

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2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

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