RPSim: SoC软件开发的快速原型全系统模拟器

Haojun Wang, Qinghao Min, Yi Li, Weihua Zhang
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引用次数: 0

摘要

如今,SoC产品的发布已经到了爆发的阶段。这些产品的上市时间已经缩短到极致,将近8到12个月。为了缩短生产周期,硬件架构师通常会在设计中结合经过良好调优的IP核。为了保证SoC软件开发的进程,最终决定产品的发布时间,在硬件设计完成后,SoC软件开发的快速原型仿真平台应该尽快可用。然而,最先进的SoC模拟器缺乏对IP核快速集成的支持,并且需要耗时的编译器链修改新指令。在本文中,我们提出Prism,一个可扩展和易于使用的全系统SoC仿真平台,用于SoC软件开发。设计和实现了两种机制,以支持新的IP核模拟或新的指令扩展的快速原型,而无需修改编译器工具链。首先,提出了一种用于IP核快速成型的软硬件混合机制。采用无缝接口消除IP核之间的差异。其次,为新指令扩展设计了可配置的库机制。寄存器依赖性可以保持详细的时序模拟,而无需修改编译器工具链。在这样的设计中,扩展的主要工作是指定精心设计的公共定制接口。实验结果表明,这些机制的运行时间开销仅为0.36%。基于RPSim,研究生只需要编写大约40行代码,不到半小时就可以在RPSim中扩展一个新的IP核模拟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
RPSim: A Rapid Prototyping Full-System Simulator for SoC Software Development
Nowadays, the release of SoC products has come to a burst. Time-to-market of these products has been shortened to an extreme, nearly 8 to 12 months. To reduce production period, hardware architects generally combine well-tuned IP cores in their designs. To guarantee the process of SoC software development, which will finally decide the release time of products, a fast prototyping simulation platform for SoC software development should be available as soon as possible after hardware design. However, state-of-the-art SoC simulators lack the support for fast integration of IP core and require time-consuming compiler chain modifications for new instructions. In this paper, we present Prism, an extensible and easy-to-use full-system SoC simulation platform for SoC software development. Two mechanisms are designed and implemented to support fast prototyping for new IP core simulation or new instruction extension without compiler tool chain modifications. First, a hardware and software hybrid mechanism is proposed for IP core fast prototyping. A seamless interface is used to eliminate the differences among IP cores. Second, a configurable library mechanism is designed for new instruction extension. Register dependence can be maintained for detailed timing simulation without compiler tool chain modification. In such a design, the major effort for extension is to specify the elaborate common customization interface. Experimental results show these mechanisms only involve about 0.36% runtime overhead. Based on RPSim, a graduate student only needs write about 40 lines of code and takes less than half an hour to extend a new IP core simulation in RPSim.
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