The impacts of base bias resistor and LTE 16QAM signal bandwidth on high-efficiency linear SiGe power amplifier design

This paper investigates the design of a linear highly-efficient SiGe power amplifier (PA) where its linearity, power-added efficiency (PAE) and P_OUT are studied vs. different LTE 16QAM signal BW and a relatively small bias resistance R_bias is used to set up the base bias from a DC voltage source in lieu of using a large choke inductor. The PA is designed in a 0.35-μm SiGe BiCMOS technology with through-silicon via (TSV), passing the stringent LTE spectrum emission mask (SEM) at average linear P_OUT = 23.5/23.1/23.1 dBm with 48.0/45.2/44.6% PAE for LTE 5/10/20 MHz inputs at R_bias = 500 Ω. However, both linearity and PAE degrade when R_bias decreases to 330 Ω or increases to 1000 Ω. The adjacent channel leakage ratios ACLR1/ACLR2 exhibit over 10-21 dB degradation at R_bias = 330 Ω and 1000 Ω for LTE 20 MHz input at P_OUT = 23.1 dBm (P_1dB = 22.3 dBm), while they are practically unchanged against R_bias for 5 MHz LTE input or at 6 dB P_OUT back-off at 17.1 dBm. Envelope-tracking (ET) is also used to improve PA's efficiency at back-off for R_bias = 500 Ω. The data suggests for SiGe PA design with TSV, a small bias R_bias may be used in lieu of a large inductor to save area, while its performance is dependent on the optimal bias R_bias value - too high or too low of R_bias will degrade its RF gain, stability and linearity for both CW and LTE modulated signal inputs.