Synthesis and Simulation of A Low-Power, High-Efficiency and Effective Dadda Multiplier

The multiplier is a crucial piece of hardware that plays a substantial role in the overall power consumption of most CPUs. The output state of this circuit is the sum of its two input signals. The two most fundamental building blocks of multipliers are a full adder and a half adder. Different design implementations of a full adder and half adder circuits have been used to produce an optimized multiplier circuit that incorporates pass transistor logic, Different multiplication algorithm strategies, such as Wallace tree multiplication, booth's algorithm, standard array multiplier, radix-4 multiplier technique, Vedic mathematics, Dadda's algorithm, and others, can also be utilized to create the multiplier. In this work we compare the result with power, delay and transistor count for different techniques and methods. One of the most efficient algorithms for low power and high speed architectures is the Dadda algorithm. The AND gate, half adder, and full adder circuits are the key building elements of the multiplier, resulting in a reduction in overall power consumption and latency. These major building blocks will be implemented using Hybrid (CMOS process and transmission gate logic) technique and GDI technique. The multiplier's efficiency will next be compared in terms of power dissipation, latency, and area using Cadence tools. And also the 4 bit multiplier is enhanced to 8 bit multiplier using the Dadda algorithm and this will be implemented in Xilinx ISE software using Verilog language and RTL schematic will be designed.