Design and performance analysis for the reversible realization of adder/subtractor circuit

Digital circuits have been basically applied to every field of life. Low power efficient systems are the need of this era. Reversible logic approach is the basic outcome of this necessity. Reversible technology is widely applicable in the field of nanotechnology, low power CM0S design, optical computing etc. Reversible approach basically aims to redesign any digital circuit with reversible design units. Here, we propose an efficient approach to design N-bit Adder/subtractor using reversible approach. Based on proposed N-bit Adder/Subtractor design we have also compared 4-bit, 8-bit and 16-bit circuits with the existing designs. Proposed designs are simulated and synthesized with Xilinx Spartan 3E for Device XC3S500E at 200 MHz frequency.