全体会议演讲2P1:电子和纳米技术的消费化:对制造测试的影响

S. Taneja
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引用次数: 0

摘要

只提供摘要形式。测试一直被认为是设计和制造之间的桥梁。然而,设计和测试工具的创新和深度集成并没有跟上电子产品消费化和快速发展的纳米集成电路设计和制造的步伐。因此,Test的全部潜力还没有被主流半导体社区所利用。电子产品的消费化对低功耗、正确性和批量生产时间提出了新的重大要求。由于先进的物理效应和更高规模的晶体管集成,纳米技术的快速发展带来了额外的挑战。EDA行业需要建立一个新的范式和“深度整合”来应对这些挑战。在设计阶段,功耗感知DFT架构必须与低功耗设计和实现流程紧密集成。随后,在制造阶段,必须无缝利用DFT的优势进行基于良率学习的快速扫描诊断,不仅使用来自设计数据库的逻辑信息,还使用布局时序和功率信息。本次主题演讲将讨论这些挑战以及可能的解决方案和场景。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Plenary Speech 2P1: Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing Test
Summary form only given. Test has long been recognized as the bridge between design and manufacturing. However, innovation and deep integration in design and test tools has not kept pace with the consumerization of electronics and the rapidly evolving nanometer IC design and manufacturing. As a result, the full potential of Test has not been harnessed by the mainstream semiconductor community.The consumerization of electronics places significant new demands on low power, correctness and time-to-volume production.The rapid advances in nanometer technologies pose additional set of challenges due to the advanced physics effects and higher scales of transistor integration. The EDA industry needs to establish a new paradigm and a "deep integration" to meet these challenges. During the design phase, a power-aware DFT architecture must integrate tightly with low power design and implementation flow. Later, during the manufacturing phase, the benefits of DFT must be seamlessly harnessed for rapid scan diagnostics based yield learning using not only logic information from the design database but also using layout timing and power information. This keynote will discuss these challenges and possible solutions and scenarios.
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