基于FPGA/CPU混合数据平面架构的深度可编程分组交换节点缓解SDN网络中的DoS攻击

Enio Kaljic, A. Maric, Pamela Njemcevic
{"title":"基于FPGA/CPU混合数据平面架构的深度可编程分组交换节点缓解SDN网络中的DoS攻击","authors":"Enio Kaljic, A. Maric, Pamela Njemcevic","doi":"10.1109/icat47117.2019.8938862","DOIUrl":null,"url":null,"abstract":"The application of the concept of software-defined networks (SDN) has, on the one hand, led to the simplification and reduction of switches price, and on the other hand, has created a significant number of problems related to the security of the SDN network. In several studies was noted that these problems are related to the lack of flexibility and programmability of the data plane, which is likely first to suffer potential denial-of-service (DoS) attacks. One possible way to overcome this problem is to increase the flexibility of the data plane by increasing the depth of programmability of the packet-switching nodes below the level of flow table management. Therefore, this paper investigates the opportunity of using the architecture of deeply programmable packet-switching nodes (DPPSN) in the implementation of a firewall. Then, an architectural model of the firewall based on a hybrid FPGA/CPU data plane architecture has been proposed and implemented. Realized firewall supports three models of DoS attacks mitigation: DoS traffic filtering on the output interface, DoS traffic filtering on the input interface, and DoS attack redirection to the honeypot. Experimental evaluation of the implemented firewall has shown that DoS traffic filtering at the input interface is the best strategy for DoS attack mitigation, which justified the application of the concept of deep network programmability.","PeriodicalId":214902,"journal":{"name":"2019 XXVII International Conference on Information, Communication and Automation Technologies (ICAT)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"DoS attack mitigation in SDN networks using a deeply programmable packet-switching node based on a hybrid FPGA/CPU data plane architecture\",\"authors\":\"Enio Kaljic, A. Maric, Pamela Njemcevic\",\"doi\":\"10.1109/icat47117.2019.8938862\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The application of the concept of software-defined networks (SDN) has, on the one hand, led to the simplification and reduction of switches price, and on the other hand, has created a significant number of problems related to the security of the SDN network. In several studies was noted that these problems are related to the lack of flexibility and programmability of the data plane, which is likely first to suffer potential denial-of-service (DoS) attacks. One possible way to overcome this problem is to increase the flexibility of the data plane by increasing the depth of programmability of the packet-switching nodes below the level of flow table management. Therefore, this paper investigates the opportunity of using the architecture of deeply programmable packet-switching nodes (DPPSN) in the implementation of a firewall. Then, an architectural model of the firewall based on a hybrid FPGA/CPU data plane architecture has been proposed and implemented. Realized firewall supports three models of DoS attacks mitigation: DoS traffic filtering on the output interface, DoS traffic filtering on the input interface, and DoS attack redirection to the honeypot. Experimental evaluation of the implemented firewall has shown that DoS traffic filtering at the input interface is the best strategy for DoS attack mitigation, which justified the application of the concept of deep network programmability.\",\"PeriodicalId\":214902,\"journal\":{\"name\":\"2019 XXVII International Conference on Information, Communication and Automation Technologies (ICAT)\",\"volume\":\"86 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 XXVII International Conference on Information, Communication and Automation Technologies (ICAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/icat47117.2019.8938862\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 XXVII International Conference on Information, Communication and Automation Technologies (ICAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icat47117.2019.8938862","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

软件定义网络(SDN)概念的应用,一方面导致了交换机的简化和价格的降低,另一方面也产生了大量与SDN网络安全相关的问题。在一些研究中指出,这些问题与数据平面缺乏灵活性和可编程性有关,这可能首先遭受潜在的拒绝服务(DoS)攻击。克服这个问题的一种可能方法是通过增加流表管理级别以下的分组交换节点的可编程性深度来增加数据平面的灵活性。因此,本文研究了在防火墙实现中使用深度可编程分组交换节点(DPPSN)体系结构的机会。然后,提出并实现了一种基于FPGA/CPU数据平面混合架构的防火墙体系结构模型。实现的防火墙支持三种DoS攻击缓解模式:输出接口DoS流量过滤、输入接口DoS流量过滤和DoS攻击重定向到蜜罐。对所实现防火墙的实验评估表明,在输入接口进行DoS流量过滤是缓解DoS攻击的最佳策略,证明了深度网络可编程性概念的应用是正确的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
DoS attack mitigation in SDN networks using a deeply programmable packet-switching node based on a hybrid FPGA/CPU data plane architecture
The application of the concept of software-defined networks (SDN) has, on the one hand, led to the simplification and reduction of switches price, and on the other hand, has created a significant number of problems related to the security of the SDN network. In several studies was noted that these problems are related to the lack of flexibility and programmability of the data plane, which is likely first to suffer potential denial-of-service (DoS) attacks. One possible way to overcome this problem is to increase the flexibility of the data plane by increasing the depth of programmability of the packet-switching nodes below the level of flow table management. Therefore, this paper investigates the opportunity of using the architecture of deeply programmable packet-switching nodes (DPPSN) in the implementation of a firewall. Then, an architectural model of the firewall based on a hybrid FPGA/CPU data plane architecture has been proposed and implemented. Realized firewall supports three models of DoS attacks mitigation: DoS traffic filtering on the output interface, DoS traffic filtering on the input interface, and DoS attack redirection to the honeypot. Experimental evaluation of the implemented firewall has shown that DoS traffic filtering at the input interface is the best strategy for DoS attack mitigation, which justified the application of the concept of deep network programmability.
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