H. Singh, Guangming Lu, E. Filho, R. Maestre, Ming-Hau Lee, F. Kurdahi, N. Bagherzadeh
{"title":"Morphosys:针对多媒体应用的可重构计算系统的案例研究","authors":"H. Singh, Guangming Lu, E. Filho, R. Maestre, Ming-Hau Lee, F. Kurdahi, N. Bagherzadeh","doi":"10.1145/337292.337583","DOIUrl":null,"url":null,"abstract":"In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications. This 2-million transistor design combines a reconfigurable array of cells with a RISC processor core and a high bandwidth memory interface. The system architecture, software tools including a scheduler for reconfigurable systems, and performance analysis (with impressive speedups) for target applications are described.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"65","resultStr":"{\"title\":\"Morphosys: case study of a reconfigurable computing system targeting multimedia applications\",\"authors\":\"H. Singh, Guangming Lu, E. Filho, R. Maestre, Ming-Hau Lee, F. Kurdahi, N. Bagherzadeh\",\"doi\":\"10.1145/337292.337583\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications. This 2-million transistor design combines a reconfigurable array of cells with a RISC processor core and a high bandwidth memory interface. The system architecture, software tools including a scheduler for reconfigurable systems, and performance analysis (with impressive speedups) for target applications are described.\",\"PeriodicalId\":237114,\"journal\":{\"name\":\"Proceedings 37th Design Automation Conference\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"65\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 37th Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/337292.337583\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 37th Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/337292.337583","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Morphosys: case study of a reconfigurable computing system targeting multimedia applications
In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications. This 2-million transistor design combines a reconfigurable array of cells with a RISC processor core and a high bandwidth memory interface. The system architecture, software tools including a scheduler for reconfigurable systems, and performance analysis (with impressive speedups) for target applications are described.