{"title":"基于转发器收缩阵列的多层神经网络实现","authors":"Q. Song, E.K. Teoh, D.P. Mital","doi":"10.1016/0165-6074(95)00010-L","DOIUrl":null,"url":null,"abstract":"<div><p>Performance analysis and comparison are carried out for the one- and two-dimensional systolic arrays based on transputers. Low efficiency has been found in the one-dimensional array because of communication overhead. The systolic algorithm is extended to the two-dimensional array to implement a full parallelism in each layer's calculation. This speeds up simulation of the network. Experiment results are provided to support the performance evaluation.</p></div>","PeriodicalId":100927,"journal":{"name":"Microprocessing and Microprogramming","volume":"41 4","pages":"Pages 289-299"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0165-6074(95)00010-L","citationCount":"2","resultStr":"{\"title\":\"Multilayered neural network implementation on transputer systolic array\",\"authors\":\"Q. Song, E.K. Teoh, D.P. Mital\",\"doi\":\"10.1016/0165-6074(95)00010-L\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>Performance analysis and comparison are carried out for the one- and two-dimensional systolic arrays based on transputers. Low efficiency has been found in the one-dimensional array because of communication overhead. The systolic algorithm is extended to the two-dimensional array to implement a full parallelism in each layer's calculation. This speeds up simulation of the network. Experiment results are provided to support the performance evaluation.</p></div>\",\"PeriodicalId\":100927,\"journal\":{\"name\":\"Microprocessing and Microprogramming\",\"volume\":\"41 4\",\"pages\":\"Pages 289-299\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1016/0165-6074(95)00010-L\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microprocessing and Microprogramming\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/016560749500010L\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microprocessing and Microprogramming","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/016560749500010L","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multilayered neural network implementation on transputer systolic array
Performance analysis and comparison are carried out for the one- and two-dimensional systolic arrays based on transputers. Low efficiency has been found in the one-dimensional array because of communication overhead. The systolic algorithm is extended to the two-dimensional array to implement a full parallelism in each layer's calculation. This speeds up simulation of the network. Experiment results are provided to support the performance evaluation.
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